1. Field of Invention
This invention relates in general to out-of-order processors, and more particularly, to a method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processor.
2. Description of Background
In out-of-order processors, instructions may execute in an order other than what the program specified. For an instruction to execute on an out-of-order processor, only three conditions need normally be satisfied:
(1) the inputs to the instruction are available;
(2) a function unit is available on which to execute the instruction;
(3) there is a place to put the result.
For most instructions, these requirements are relatively straight-forward. However, for load instructions, accurately determining condition (1) is difficult. Load instructions have two types of inputs: (1) registers, which specify the address from which data is to be loaded, and (b) the memory location(s) from which the load data will come. Determining the availability of register values in case (a) is relatively straight-forward. However, determining the availability of memory locations in case (b) is not. The problem with memory locations is that there may be stores earlier in program order than a particular load and some of these stores may not have executed, when the remaining parts of the three conditions above are satisfied, for example, (1) when all of the register inputs for the load instruction are ready, (2) there is a function unit available on which the load can be executed, and (3) there is a place (a register) in which to put the loaded value. Since earlier stores have not executed, it may be that the data locations to which these stores write, are some of the same data locations from which the load reads. In general, without executing the store instructions, it is not possible to determine if the address (data locations) to which a store writes overlap the address from which a load reads.
As a result, most modern out-of order processors execute load instructions when (1) all of the input register values are available, (2) there is a function unit available on which to execute the load, and (3) there is a register where the loaded value may be placed. Since dependences on previous store instructions are ignored, a load instruction may sometimes execute prematurely, and have to be squashed and re-executed so as to obtain the correct value produced by the store instruction.
To detect when a load instruction has executed prematurely, modern processors typically have a load reorder queue (LRQ), which keeps a list of all in-flight loads. In-flight loads have been fetched and decoded by the processor, but have not fully completed their execution, or are waiting on older instructions in the program to finish their execution. Completed means that the loads have finished executing, and thus each of these instructions can be represented to the programmer or anyone else viewing execution of the program as having completed their execution.
The LRQ list is normally sorted by the order of loads in the program. Each entry in the LRQ has, among other information, the address(es) from which the load received data.
Each time a store executes, it checks the LRQ to determine if any loads which are after the store in program order, nonetheless executed before the store, and if so, whether any of those loads read data from a location to which the store writes. If so, the store signals the appropriate parts of the processor that the load has received a bad value and must re-execute.
More importantly for this invention are the related problems that arise when a processor is one of a plurality of processors in a multiprocessor (MP) system. Different MP systems have different rules for the ordering of load and store instructions executed on different processors. At a minimum, most MP processors require a condition known as sequential load consistency. Which means that if processor X stores to a particular location A, then all loads from location A on processor Y must be consistent. In other words, if an older load in program order on processor Y sees the updated value at location A, then any younger load in program order on processor Y must also see that updated value.
If all of the loads on processor Y were executed in order, such sequential load consistency would happen naturally. However, on an out-of-order processor, the younger load in program order may execute earlier than the older load in program order. If processor X updates the location from which these two loads read, then sequential load consistency will be violated.
To avoid problems with sequential load consistency, each time a processor writes to a particular location, it conceptually informs every other processor that is has done so. In practice, most processor systems have mechanisms which avoid the need to inform every processor of every individual store performed by other processors.
These mechanisms for avoiding notification to each processor of every store performed on every other processor, typically center on having a coherence point in the hierarchy of caches serving the processor. The cache closet to the processor is typically labeled the level 1, or L1 cache, the next closet cache the L2, etc. The coherence point in the cache hierarchy is informed of all locations that may be stored to by other processors, but cache levels nearer to the processor than the coherence point are not informed unless they actually contain data being updated by another processor. Typically the coherence point in a multiprocessor system is at the L2 or L3 cache level.
However this approach poses difficulties for processors which employ a technique known as simultaneous multi-threading (SMT). In SMT, a single processor executes multiple threads, possibly sharing data. Each of the threads in an SMT processor acts much like an independent processor in a multi-processor system. In particular, the stores from one thread must be conceptually passed to every other thread in the processor as well as to every other processor in the system. However, all of the SMT threads in a processor share the closest L1 cache level. Because of this, a more distant cache level like L2 or L3 cannot be used as a coherence point to filter out stores from other threads on the same processor. As a result, every thread in the processor must pay attention to the stores from every other thread in the processor.
Paying attention to every store from every other thread in the processor can be expensive. To illustrate the point, consider how processors deal with the filtered, and relatively small number of snoops coming from other processors. When a processor Y receives a notice (a snoop) that another processor X has written to a location, processor Y must ensure that all of the loads currently in-flight receive sequentially load consistent values. The check to ensure this condition is similar to the check described above for store instructions: each entry in the LRQ is checked to see if it matches the address stored to by the other processor X.
All entries in the LRQ, which match the snoop address have a snooped bit set to indicate that they match the snoop. All load instructions check this snooped bit when they execute. More precisely, when a load instruction (L) executes, it checks all entries in the LRQ to see if there are any load instructions (M) which satisfy all of the following conditions:
(1) load M is younger in program order than the current load L;
(2) load M is from the same address as the current load L;
(3) load M has already executed;
(4) load M has the snooped bit set.
Any load M in the LRQ meeting all of these conditions must re-execute so as to maintain sequential load consistency, for example, to ensure that the younger load Y does not receive an older value than the older load L.
Given the filtering done by the coherence point in the cache for stores done by other processors, the rate at which snoops arrive at a processor and require such processing is typically one snoop every few hundred to every few thousand cycles.
However, in SMT processors with no such filtering from the coherence point and 1 to 7 or more other threads running on the same processor, there are likely to be multiple stores per cycle for which these snoop checks must be performed.
To facilitate such checks, additional ports are needed for the LRQ, and each such port consumes significant area and power. Additional ports also tend to reduce the speed at which the LRQ may be accessed, thus, potentially reducing the frequency at which the processor may run.
The porting requirement for snoops from other threads is not the only problem. There may be many loads in-flight at any one time: modern processors allow 16, 32, 64 or more loads to be simultaneously in-flight. Thus, a load instruction or a snoop must check 16, 32, 64 or more entries in the LRQ to ensure that no loads execute prematurely.
Since new load instructions may occur each cycle in a modern processor, these checks for premature load execution must take at most one cycle, for example, all 16, 32, 64 or more entries in the LRQ must be able to be checked every cycle. Such a fully associative comparison is known to be expensive (a) in terms of the area required to perform the comparison, (b) in terms of the amount of energy required to perform the comparison, and (c) in terms of the time required to perform the comparison, for example, a cycle may have to take longer than it otherwise would so as to allow time for the comparison to complete.
All three of these factors (a), (b) and (c) are significant concerns in the design of modern processors, and improved solutions, such as what is proposed here, are important to continued processor improvement.
The standard solution to limiting the cost of LRQ checking for sequential load consistency is to limit the number of entries in the LRQ, so as to stay within area, power, and cycle time constraints.
Limiting the number of entries in the LRQ limits the number of possible instructions in flight. Out-of-order processors achieve significant performance gains by their ability to execute from a large window of instructions, the larger the window, the more likely that an instruction can be found which has available all of the inputs needed to execute. Thus, the limit placed on LRQ size limits the window of instructions for execution, and thus limits the performance of the processor.
Thus, a solution which checks fewer entries in the LRQ, thus allowing a larger LRQ could contribute to improved performance in an out-of-order processor.